Semiconductor Engineering: Promises and Pitfalls of SoC Restructuring
by On Jun 25, 2024
Sidestepping data incompatibility issues in heterogeneous chip designs.
As chips become more complex and increasingly heterogeneous, it’s becoming more difficult to keep track of different methodologies, tools, and blend data from different sources to create a chip. Tim Schneider, staff application engineer at Arteris, explains why IP-XACT has become so critical, why it took so long to gain a solid foothold in chip design, and how the new IP-XACT standard interfaces with SystemVerilog.
To watch the video on SemiEngineering, click here.
